A system provides ultra-low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL, and DDS (Direct Digital Synthesizer).
 Embodiments of the present disclosure are generally related to systems to provide ultra-low phase noise frequency synthesizers and, in particular, connect to plans to offer ultra-low phase noise frequency synthesizers based on using a combination of Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer).
 Wireless Communication Technologies have revolutionized how millions of people in today’s world seamlessly communicate.
From their early infant days of the late 1800s till today, the concept of wireless communications has matured beyond our wildest imaginations. Amongst all those technological advances related to wireless communication technologies, the only thing which has remained constant is the application of radio waves. On the one hand, radio waves can help us communicate with people located close to a few meters. In the same manner in deep space radio communications, those same radio waves can also help us achieve crystal-clear communication between humans who are millions of kilometers away.
 Wireless Communication Technologies have branched into multiple formats like Two-Way Radio Communications, Satellite Communications, Infrared Communications, Mobile Communications, Microwave Communications, Wireless Data Communications, Wi-Fi, Bluetooth Technology, etc. Each of the above-disclosed wireless communication technologies has evolved tremendously and become much more sophisticated and state-of-the-art. In this patent application, we will specifically deal with systems associated with Mobile Communications.
 The evolution of mobile communication technologies from their initial 1 G (1 Generation) days of 1970 till 2016, which is today’s high-speed 4G (4 Generation) technologies, have enriched human lives in different shapes and sizes. The most significant impact these gradual evolutions of mobile communication technologies have brought into our lives is the humongmassivease in data speed, enabling seamless communications between millions of people. Where 1 G technology-enabled communication systems provide simple voice communications at only a 10 Kbps data rate, the theoretical download data rate of the most advanced mobile communication technologies as of 2016 is LTE- Advanced (Long Term Evolution), which has been proposed as 1 Gbps. This quantum jump in data rate from 10 Kbps to 1 Gbps has significantly impacted familiar people’s lives.
 With the availability of advanced state-of-the-art communication systems in today’s markets like smasmartphonest is possible to access those high-speed data rates. One of the essential hardware elements present in those state-of-the-art systems, like smartphones, is frequency synthesizers. Frequency Synthesizers are a significant building block in almost every communication system, such as advanced mobile communication systems (LTE, LTE-Advanced), satellite communication systems, radar communication systems, and so on.
 An example frequency synthesizer provides a frequency output signal to other parts of the transmitter and receiver, enabling the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. The main important features of every synthesizer are a) Output frequency range, b) Output frequency resolution, c) Switching speed between channels, and d) Spectral purity: Phase noise, spurious and harmonics, etc. Amongst all the features mentioned above, phase noise is the most important. The level of phase noise determines the modulation scheme that can be implemented in the system hardware and thus determines the systems’ associated data rates and communication ranges.
 If a communication system provides a higher data rate, it is more efficient and takes less time to download and upload data from the network. A higher data transfer rate can save battery time because the transmission can be turned off much faster. A higher-order modulation scheme implemented in state-of-the-art communication systems enables those systems to push more information into the wireless channels. However, the modulation scheme is limited by phase noise. Hence to implement those higher modulation schemes in the existing state-of-the-art communication systems, we need to reduce the phase noise.
 Modern communication systems use sophisticated modulation schemes based on different phases and amplitudes. Most smartphones or tablets’ most advanced modulation scheme is 256 QAM (256 Quadrature Amplitude Modulation). Theoretically, this modulation scheme’s smallest phamost minortion for error (Δ0) is 3.7°. To be on the safe side, working with a lower number is desired, as 10% is considered safe. Hence the current generation of frequency synthesizers works with 0.4°- 0.5°. The current generation of single-loop frequency synthesizers inherently does not enable much lower phase error due to phase noise.
 The current generation of advanced state-of-the-art communication systems typically includes a front-end module and a System on Chip (SoC). The frequency synthesizer is part of the SoC and is implemented mainly in CMOS. The front-end module usually contains a low noise amplifier for the receiver, a power amplifier for the transmitter, and some switch matrix. The SoC includes all the signal-processing elements along with the frequency synthesizers. Currently, the Wi-Fi and LTE synthesizers in the SoC set the limit for the system’s performance. As a result, the multi-billion dollar market remains at a technological standstill.
 Further, in many communication systems, Digital Pre-Distortion (DPD) is an algorithm aiming to pre-distort transmitted signals to improve linearity. In practical terms, the transmitter is not entirely linear and distorts the signal. And that prevents the system from being as effective as possible. So one approach to correct it is by using some algorithms to pre-distort the password in the opposite way. To do this efficiently, the DPD algorithm requires the amplitude and phase data about the transmitted data.
 Traditional radio systems either utilize the receive path of the radio or a unique down-conversion mechanism followed by a high-resolution analog-to-digital converter to capture the small non-linearities of the transmit path. The main problem with the above tool is that non-linearities and phase noise of the receive path or particular down-conversion path get added to the signal, and the DPD algorithm cannot separate the non-linearities and the phase noise generated and added during the down-conversion from the ones that were created in the transmit path and need correction.
 The transmit path nonlinearities; can come from any component, such as a low-frequency amplifier, mixer, up-converter, and driver amplifier. Specifically, the Power Amplifier (PA) is the primary source of nonlinear distortions in the transmit path, and the main goal of the DPD algorithm is to pre-distort this to achieve a cleaner signal. As mentioned above, all the receive path nonlinearities are added to the transmit path with no way to distinguish between the two.
 Hence, there is a need for a low-phase noise frequency synthesizer that can overcome prior art problems, enable higher modulation schemes and high data rate by reducing phase noise, resolve the locking problem in the sampling PLLs and minimize DPD distortions in received signals. The target of the present disclosure is to enable a much lower level of phase deviation for error (Δ0) which should be in the range of 10% of current designs, or 0.04°. Thus, it enables much higher-order modulation schemes and an efficient DPD algorithm.
 I want to point out that the present disclosure discusses state-of-the-art wireless communication systems (smartphones) for exemplary purposes only.
The present disclosure applies to any state-of-the-art wireless communication system enabling consumers to communicate seamlessly.
 According to the first embodiment of the present disclosure, a system comprising one ultra-low phase noise frequency synthesizer is provided. The method consists of a front-end module, a display screen, and one System on Chip (SoC) module. The ultra-low phase noise frequency synthesizer is part of the SoC module. The ultra-low phase noise frequency synthesizer comprises one main PLL (Phase Lock Loop) and one reference sampling PLL. The main PLL shall consist of one high-frequency DDS (Direct Digital Synthesizer), one Digital Phase Frequency Detector, one primary VCO (Voltage Controlled Oscillator), one frequency divider, and one down convert mixer. The reference sampling PLL comprises one TCXO (Temperature Compensated Crystal Oscillator), one sampling phase detector, and one reference VCO. This embodiment provides multiple improvements in system output which are based on the following technical approaches – a) using of dual loop approach to reduce frequency multiplication number, b) using of sampling PLL as the reference PLL to make its noise contribution negligible, c) using of DDS to provide high-frequency input to the main PLL and d) using of high-frequency Digital Phase Frequency Detector in the main PLL.
 According to a second embodiment of the present disclosure, a system comprising one ultra-low phase noise frequency synthesizer is provided. The method consists of a front-end module, a display screen, and one System on Chip (SoC) module. The ultra-low phase noise frequency synthesizer is part of the SoC module. The ultra-low phase noise frequency synthesizer comprises one main PLL (Phase Lock Loop) and one reference sampling PLL. The ultra-low phase noise frequency synthesizer shall consist of one single TCXO (Temperature Compensated Crystal Oscillator), which provides input clock signals to both the main PLL and the reference sampling PLL. The main PLL comprises one Fractional-N Synthesizer chip, one primary VCO (Voltage Controlled Oscillator), and one down convert mixer. The Fractional-N Synthesizer chip includes one Digital Phase Detector and one software-controllable variable frequency divider. The reference sampling PLL comprises one sampling PLL and one reference VCO. This embodiment provides multiple improvements in system output which are based on the following technical approaches – a) using of dual loop approach to reduce frequency multiplication number, b) using of sampling PLL to make its noise contribution negligible, c) instead of a DDS clock like in the previous embodiment, using of a high-frequency TCXO clock to provide high-frequency input to the main PLL, and d) using of a high-frequency Fractional-N Synthesizer chip in the main PLL.
 According to a third embodiment of the present disclosure, a system comprising one ultra-low phase noise frequency synthesizer is provided. The method consists of a front-end module, a display screen, and one System on Chip (SoC) module. The ultra-low phase noise frequency synthesizer is part of the SoC module. The system comprises one sampling PLL (Phase Lock Loop), one of the essential building blocks of an ultra-low phase noise frequency synthesizer. The sampling PLL includes one TCXO (Temperature Compensated Crystal Oscillator), one Comb Generator, one Sampling Phase Detector, one DC switch, one Loop Filter, one VCO (Voltage Controlled Oscillator), and one Digital Synthesizer. In this embodiment, the loop filter is just a loop filter. The Digital Synthesizer acts as a phase detector when the loop is locked and a frequency detector when the coil is open, forcing the loop to lock from any distance between the two frequencies. The circle will lock by the Digital Synthesizer. Once it is closed, the lock indicator will switch the PLL to the sampling PLL while keeping the same control voltage, thus keeping the loop shut.
 The following is a simplified summary to help you understand some aspects of the present disclosure. This summary is neither an extensive nor exhaustive overview of the present disclosure and its various embodiments. The summary presents selected concepts of the embodiments of the present disclosure in a simplified form as an introduction to the more detailed description shown below. As will be appreciated, other embodiments of the present disclosure are possible using, alone or in combination, one or more of the features set forth above or described in detail below.