US 9762251 Ultra-low phase noise frequency synthesizer
ABSTRACT – A system for providing ultra-low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing a much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.
Embodiments of the present disclosure is generally related to systems to provide ultra low phase noise frequency synthesizer and in particular relate to systems to provide ultra low phase noise frequency synthesizer based on using combination of Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer).
Wireless Communication Technologies have completely revolutionized how millions of peoples in today’s world are communicating with each other in a seamless manner. From their early infant days of late 1800’s till today the concept of wireless communications has matured beyond our wildest imaginations. Amongst all those technological advances related to the field of wireless communication technologies, the only thing which has remained constant is the application of radio waves. On one hand, radio waves can help us achieve communication between people who are located in close proximity of a few meters. In the same manner in deep space radio communications, those same radio waves can also help us achieve crystal clear communication between humans who are millions of kilometers away from each other.
Wireless Communication Technologies have branched into multiple different formats like Two-Way Radio Communications, Satellite Communications, Infrared Communications, Mobile Communications, Microwave Communications, Wireless Data Communications, Wi-Fi, Bluetooth Technology etc. Each and every single one of the above disclosed wireless communication technologies have evolved tremendously and become much more sophisticated and state of the art. In this patent application, we will specifically deal with systems associated with Mobile Communications.
The evolution of mobile communication technologies from their initial 1G (1 Generation) days of 1970 till 2016 which is today’s high-speed 4G (4 Generation) technologies have enriched human lives in different shapes and sizes. The biggest impact which these gradual evolutions of mobile communication technologies have brought into our lives is the humongous increase in data speed which has enabled seamless communications between millions of peoples. Where 1G technology enabled communication systems used to provide us simple voice communications at only 10 Kbps data rate, the theoretical download data rate of the most advanced mobile communication technologies as of 2016 which is LTE-Advanced (Long Term Evolution) has been proposed as 1 Gbps. This quantum jump in data rate from 10 Kbps to 1 Gbps has left a tremendous impact into common peoples’ lives.
Without the availability of the advanced state of the art communication systems in today’s markets like smartphones, it is not at all possible to access those high-speed data rates. One of the most important hardware element present in those state of the art systems like smartphones are frequency synthesizers. Frequency Synthesizers are a major building block in almost every communication systems, such as advanced mobile communication systems (LTE, LTE-Advanced), satellite communication systems, radar communication systems and so on.
An example frequency synthesizer provides a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. The main important features of every synthesizer are: a) Output frequency range, b) Output frequency resolution, c) Switching speed between channels and d) Spectral purity: Phase noise, spurious and harmonics etc. Amongst all those above-mentioned features phase noise is the most important. The level of phase noise determines the modulation scheme that can be implemented in the system hardware and thus it determines the associated data rates and the communication ranges of the systems.
If a communication system provides a higher data rate the system is more efficient, and it takes less time to download and upload data from the network. A higher data transfer rate can even save battery time because the transmission can be turned off much faster. A higher order modulation scheme implemented in the state of the art communication systems enables those systems to push more information in the wireless channels. However, the modulation scheme is limited by phase noise. Hence to implement those higher modulation schemes in the existing state of the art communication systems we need to reduce the phase noise.
Most modern communication systems use sophisticated modulation schemes that are based on a combination of different phases and amplitudes. The current most advanced modulation scheme which is running in most of the smartphones or tablets is 256 QAM (256 Quadrature Amplitude Modulation). In this modulation scheme, the smallest phase deviation for error (Δø) theoretically is 3.7°. Practically, to be on the safe side, it is desired to work with a nicely lower number. As 10% is considered safe, hence the current generation of frequency synthesizers work with 0.4°-0.5°. The current generation of single loop frequency synthesizers inherently does not enable to go to much lower phase error due to phase noise.
The current generation of advanced state of the art communication systems typically includes a front end module and a System on Chip (SoC). The frequency synthesizer is part of the SoC and is implemented mostly in CMOS. The front end module usually contains a low noise amplifier for the receiver, the power amplifier for the transmitter and some switch matrix. The SoC includes all the signal processing elements along with the frequency synthesizers. Currently, the Wi-Fi and/or LTE synthesizers in the SoC set the limit for the performance of the system. As a result, the multi-billion dollar market remains at a technological standstill.
Further, in many communication systems, Digital Pre-Distortion (DPD) is an algorithm that aims to pre-distort transmitted signals in order to improve linearity. In practical terms, it means that the transmitter is not completely linear and is distorting the signal. And that basically also prevents the system to be as effective as much as possible. So one approach is to correct it is by using some algorithms to pre-distort the signal in the opposite way. To do this efficiently, the DPD algorithm requires the amplitude and phase data about the transmitted data.
Traditional radio systems either utilize the receive path of the radio or a special down-conversion mechanism followed by a high-resolution analog to digital converter to capture the small non-linearities of the transmit path. The main problem with the above mechanism is that non-linearities and phase noise of the receive path or special down-conversion path get added to the signal and the DPD algorithm cannot separate the non-linearities and the phase noise generated and added during the down-conversion from the ones that were actually created in the transmit path and need correction.
The transmit path nonlinearities; can come from any component such as a low-frequency amplifier, mixer, up-converter, driver amplifier. Specifically, the Power Amplifier (PA) is the main source of nonlinear distortions in the transmit path and the main goal of the DPD algorithm is to pre-distort this to achieve a cleaner signal. As mentioned above all the receive path nonlinearities are added to the transmit path with no way to distinguish between the two.
Hence, there is a need for a low phase noise frequency synthesizer that can overcome the problems of prior art, enable higher modulation schemes and high data rate by reducing phase noise, resolve the locking problem in the sampling PLLs and minimize DPD distortions in received signals. The target of the present disclosure is to enable much lower level of phase deviation for error (Δø) which should be in the range of 10% of current designs, or 0.04° and thus enables much higher order modulation schemes and enables an efficient DPD algorithm.
The present disclosure is discussed in reference to state of the art wireless communication systems (smartphones) for exemplary purposes only. It is contemplated that the present disclosure is applicable to any state of the art wireless communication systems which enables consumers to communicate with each other in a seamless manner.
According to a first embodiment of the present disclosure, a system comprising one ultra-low phase noise frequency synthesizer is provided. The system is made up with a front-end module, a display screen and one System on Chip (SoC) module. The ultra-low phase noise frequency synthesizer is part of the SoC module. The ultra-low phase noise frequency synthesizer comprises one main PLL (Phase Lock Loop) and one reference sampling PLL. The main PLL comprises one high-frequency DDS (Direct Digital Synthesizer), one Digital Phase Frequency Detector, one main VCO (Voltage Controlled Oscillator), one frequency divider and one down convert mixer. The reference sampling PLL comprises one TCXO (Temperature Compensated Crystal Oscillator), one sampling phase detector, and one reference VCO. This embodiment provides multiple improvements in system output which are based on the following technical approaches—a) using of dual loop approach to reduce frequency multiplication number, b) using of sampling PLL as the reference PLL to make its noise contribution negligible, c) using of DDS to provide high frequency input to the main PLL and d) using of high frequency Digital Phase Frequency Detector in the main PLL.
According to a second embodiment of the present disclosure, a system comprising one ultra-low phase noise frequency synthesizer is provided. The system is made up with a front-end module, a display screen and one System on Chip (SoC) module. The ultra-low phase noise frequency synthesizer is part of the SoC module. The ultra-low phase noise frequency synthesizer comprises one main PLL (Phase Lock Loop) and one reference sampling PLL. The ultra-low phase noise frequency synthesizer comprises one single TCXO (Temperature Compensated Crystal Oscillator) which provides input clock signals to both the main PLL and the reference sampling PLL. The main PLL further comprises one Fractional-N Synthesizer chip, one primary VCO (Voltage Controlled Oscillator) and one down convert mixer. The Fractional-N Synthesizer chip includes one Digital Phase Detector and one software controllable variable frequency divider. The reference sampling PLL comprises one sampling PLL and one reference VCO. This embodiment provides multiple improvements in system output which are based on the following technical approaches—a) using of dual loop approach to reduce frequency multiplication number, b) using of sampling PLL to make its noise contribution negligible, c) instead of a DDS clock like in the previous embodiment, using of a high frequency TCXO clock to provide high frequency input to the main PLL, and d) using a high-frequency Fractional-N Synthesizer chip in the main PLL.
According to a third embodiment of the present disclosure, a system comprising one ultra-low phase noise frequency synthesizer is provided. The system is made up with a front-end module, a display screen and one System on Chip (SoC) module. The ultra-low phase noise frequency synthesizer is part of the SoC module. The system comprises one sampling PLL (Phase Lock Loop), which is one of the most important building blocks of an ultra-low phase noise frequency synthesizer. The sampling PLL comprises one TCXO (Temperature Compensated Crystal Oscillator), one Comb Generator, one Sampling Phase Detector, one DC switch, one Loop Filter, one VCO (Voltage Controlled Oscillator) and one Digital Synthesizer. In this embodiment, the loop filter is just a loop filter. The Digital Synthesizer acts as a phase detector when the loop is locked and as a frequency detector when the loop is open, forcing the loop to lock from any distance between the two frequencies. The loop will lock by the Digital Synthesizer. Once it is locked, the lock indicator will switch the PLL to the sampling PLL while keeping the same control voltage, thus keeping the loop locked.
The preceding is a simplified summary to provide an understanding of some aspects of embodiments of the present disclosure. This summary is neither an extensive nor exhaustive overview of the present disclosure and its various embodiments. The summary presents selected concepts of the embodiments of the present disclosure in a simplified form as an introduction to the more detailed description presented below. As will be appreciated, other embodiments of the present disclosure are possible utilizing, alone or in combination, one or more of the features set forth above or described in detail below.